1. Field of the Invention
This invention relates to an oscillator circuit and, more particularly, to an oscillator circuit generating an oscillation signal in response to, in a first mode, a resonant element such as a crystal and, in a second mode, an external clock signal.
2. Description of the Related Art
An example of such a conventional oscillator circuit is shown in FIG. 13. This circuit is constituted of an inverter circuit consisting of a P-type MOSFET M1 and an N-type MOSFET M2 and having an input node connected to a terminal V.sub.1 and an output node connected to a terminal V.sub.2, a transfer circuit consisting of a P-type MOSFET M3 having its drain connected to the terminal V.sub.1 and its source connected to the terminal V.sub.2 and an N-type MOSFET M4 having its drain connected to the terminal V.sub.1 and its source connected to the terminal V.sub.2, an N-type MOSFET M8 connected between the terminal V.sub.1 and the ground, an inverter circuit 11 having its input connected to the terminal V.sub.2 and its output connected to the output V.sub.0 of the oscillator circuit, and an oscillation control circuit consisting of an inverter circuit 12 and a NOR circuit 13. A crystal X1 is optionally connected between the terminal V.sub.1 and the terminal V.sub.2. In addition, the oscillator circuit includes a stop input signal V.sub.S and a switching input terminal V.sub.X from a data processing unit such as a CPU (not shown).
This circuit operates as a crystal oscillator circuit when both of the oscillation stop input signal V.sub.S and the oscillation switching input signal V.sub.X are at the low level. This is because the N-type MOSFET M8 is turned off and both of the P-type MOSFET M3 and the N-type MOSFET M4 are turned on.
On the other hand, when the signal V.sub.S is at the high level, the N-type MOSFET M8 is turned on because of the high level of its gate, and the transfer circuit is turned off by the shift of the gate of the P-type MOSFET M3 to the high level and the gate of the N-type MOSFET M4 to the low level, which brings the terminal V.sub.1 to the low level and the terminal V.sub.2 to the high level, stopping the oscillation.
The frequency-gain characteristic of the inverter circuit consisting of the P-type MOSFET M1 and the N-type MOSFET M2 is as shown in FIG. 14(a), so that oscillation is possible at a frequency lower than frequency f.sub.0 where the gain becomes 0 dB. Since the frequency f.sub.0 varies substantially in proportional to the gate width W of the MOSFET as shown in FIG. 14(b), the frequency f.sub.0 has to be selected somewhat higher than a desired oscillation frequency.
Since, however, at that time the consumed current I of the inverter circuit constituted of the P-type MOSFET M1 and the N-type MOSFET M2 is determined by the gate width W of the MOSFET with substantially proportional relation between the consumed current and the gate width as shown in FIG. 14(c), the gate width W should not be taken so large in order to reduce the power consumption. Therefore, a gate width W which gives rise to a frequency f.sub.0 slightly higher than the desired frequency is adopted.
In this oscillator circuit, the gain of the inverter circuit consisting of the P-type MOSFET M1 and the N-type MOSFET M2 decreases with the increasing load capacity C.sub.L as shown by the dependence of the load capacity on the gain as given in FIG. 15. When the oscillator circuit is operated for this reason by an external clock signal rather than by the use of the crystal oscillator, the P-type MOSFET M3 and the N-type MOSFET M4 are turned off by bringing the signal V.sub.X of the oscillation control circuit to the high level and an external clock signal V.sub.C is applied to the terminal V.sub.1 alone. In that case, the clock signal V.sub.C is transmitted to the interior of the oscillator circuit through the inverter circuit constituted of the P-type MOSFET M1 and the N-type MOSFET M2 and the inverter circuit 11.
If in this case a load capacity C.sub.L exists at the terminal V.sub.2 due to wiring pattern or the like in the exterior of the LSI, the gain decreases as shown in FIG. 15, and the external clock signal is attenuated by the inverter circuit constituted of the P-type MOSFET M1 and the N-type MOSFET M2, resulting sometimes in a situation where the transmission of the signal to the interior fails.
Moreover, if the external clock signal V.sub.C is applied to the terminal V.sub.2 alone, the output voltage of the P-type MOSFET M1 and the N-type MOSFET M2 competes with the external clock signal V.sub.C, and results either in non-transmission of the external clock signal V.sub.C to the interior or a situation in which the MOSFETs become the sources of the noise due to the flow of a high through current.
For this reason, in operating the oscillator circuit by an external clock signal, it would be necessary to externally install an inverter circuit 15 between the terminal V.sub.1 and the terminal V.sub.2, as shown in FIG. 16.